Optical lithography has been the workhorse to continuously shrink (or scale) semiconductor devices and their related interconnect structures. Traditional scaling by optical lithography has been achieved with one single exposure mostly by reduction in the wavelength of the light sources, new tool design (higher numerical aperture or NA), improved lithographic materials or a combination thereof. Recently, multiple patterning, particularly double patterning techniques, where one particular level of circuitry is patterned by exposing the wafer to a light source using two mask sets, has become increasingly necessary to maintain the pace of scaling at 193 nm optical wavelength. Typical double patterning (or pitch splitting) techniques, also referred to as double-exposure, double-etch schemes, require a lithographic imaging step, followed by a dry reactive ion etch (RIE) step into a sacrificial hardmask, followed by a second lithographic step, and yet a second RIE step into the hardmask. Finally, the double patterned images in the hardmask are transferred to the underlying substrate.
An improvement over this double patterning scheme is referred to as a double-exposure, single-etch scheme. The double-exposure, single-etch scheme achieves improved resolution by two independent exposures to form a double patterned image in a single patterning film stack and thereafter the double patterned image is transferred into the underlying substrate utilizing a single etch. This double-exposure, single-etch process scheme is as follows: A first pattern is formed into a first photoresist film by a high-resolution lithographic processes known in the art. Next, a second photoresist is coated directly on top of the first pattern. The coating of the second photoresist does not degrade the first pattern since a proper solvent for the second photoresist is employed or an image stabilization process to treat the first pattern such as, for example, thermal cure, ultraviolet cure, or surface coating, is employed. A second pattern is then formed in the second photoresist to achieve pitch splitting and thus higher resolution. Finally, an integrated reactive ion etch is performed in which both the first and second photoresist patterns are transferred into the underlying film stack.
The above mentioned double patterning scheme necessitates a significant increase in complexity, additional materials and tools, and the attendant increased manufacturing costs compared with a single exposure technique. Furthermore, the aforementioned double patterning scheme requires precise placement of the second exposure over the patterns formed by the first exposure. Any imperfect placement, or mis-alignment or overlay error, can cause degradation in performance or reliability or both of the resultant computer chips. Such mis-alignment is due to the limitation of the lithographic tool employed or processing errors.
The present disclosure the problems associated with prior art double patterning and double-exposure, single etch patterning schemes with a single-exposure, no-etch, self-aligned pitch splitting process using a hybrid photo-patternable dielectric material.